The present invention concerns the transfer of data from a first network through a bridge to a second network.
A network bridge connects two networks and facilitates the transfer of data between the networks. Typically when a personal computer acts as a network bridge, interface boards for each network are inserted into a backplane of the personal computer. On the board for each network is a direct memory access (DMA) controller consisting of a front-end processor and memory. The DMA controllers use an input/output (I/O) bus to access a main memory also connected to the I/O bus. A system processor within the personal computer also accesses the main memory through the I/O bus in order to control data transfer between the networks.
One problem with the above-described prior art system is the delay in the transfer of data between the networks introduced by the use of a standard I/O bus. This delay is caused by a number of factors. For example, I/O busses are typically designed such that the system processor uses the I/O bus a large percentage of time, lessening the time other entities such as DMA controllers are able to use the bus. The bus cycle usually matches the timing of an I/O cycle of the system processor or DMA controller. Also, a personal computer typically has as many as ten backplane slots. The necessary handshaking protocol and power requirements to drive lines for ten backplane slots additionally reduces the speed of operation of the I/O bus. In addition, delay is typically introduced by the use of local buffers between DMA controllers and the networks.